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Reducing the pressure on routing resources of FPGAs with generic logic chains.

, , , and . FPGA, page 237-246. ACM, (2011)

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A flexible DSP block to enhance FPGA arithmetic performance., , , , , and . FPT, page 70-77. IEEE Computer Society, (2009)Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs., , , , , , , and . FPGA, page 181-190. ACM, (2008)Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs., and . FPL, page 225-231. IEEE Computer Society, (2011)A novel FPGA logic block for improved arithmetic performance., , and . FPGA, page 171-180. ACM, (2008)Efficient synthesis of compressor trees on FPGAs., , and . ASP-DAC, page 138-143. IEEE, (2008)Enhancing FPGA Performance for Arithmetic Circuits., , , and . DAC, page 334-337. IEEE, (2007)Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance., and . FCCM, page 229-236. IEEE Computer Society, (2010)CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design., , , and . DFT, page 1-6. IEEE Computer Society, (2017)Exploration of approximate multipliers design space using carry propagation free compressors., , , and . ASP-DAC, page 611-616. IEEE, (2018)Closing the Gap between FPGA and ASIC - Balancing Flexibility and Efficiency.. EPFL, Switzerland, (2012)