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W for AI-Edge Devices.

W. Khwa, P. Wu, J. Wu, J. Su, H. Chen, Z. Ke, T. Chiu, J. Hsu, C. Cheng, Y. Chen, C. Lo, R. Liu, C. Hsieh, K. Tang, and M. Chang. ISSCC, page 568-570. IEEE, (2024)

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Chung-Chuan Chen

Shih-yu Chuang

Jen-Yang Chuang

Mei-Ling Chuang

Jing-Jing Chuang

Other publications of authors with the same name

POPPINS: A Population-Based Digital Spiking Neuromorphic Processor with Integer Quadratic Integrate-and-Fire Neurons.Z. Yeh, C. Hsu, C. Yeh, W. Wu, C. Wang, C. Lo, and K. Tang. ISCAS, page 1-5. IEEE, (2021)Neuromorphic luminance-edge contextual preprocessing of naturally obscured targets.A. White, C. Hung, A. Harrison, and C. Lo. ICONS, page 36:1-36:8. ACM, (2023)8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.J. Su, P. Lu, P. Wu, Y. Chou, T. Liu, Y. Chung, L. Hung, J. Ren, W. Huang, C. Chien and 11 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2304-2308 (April 2024)An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips.P. Wu, J. Su, Y. Chung, L. Hong, J. Ren, F. Chang, Y. Wu, H. Chen, C. Lin, H. Hsiao and 10 other author(s). IEEE J. Solid State Circuits, 59 (7): 2297-2309 (July 2024)Flyintel - a Platform for Robot Navigation based on a Brain-Inspired Spiking Neural Network.H. Yao, H. Huang, Y. Huang, and C. Lo. AICAS, page 219-220. IEEE, (2019)A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel.T. Hsu, Y. Chen, M. Chiu, G. Chen, R. Liu, C. Lo, K. Tang, M. Chang, and C. Hsieh. IEEE J. Solid State Circuits, 56 (8): 2516-2524 (2021)A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices.T. Wen, J. Hung, H. Hsu, Y. Wu, F. Chang, C. Li, C. Chien, C. Su, W. Khwa, J. Wu and 8 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices.W. Khwa, P. Wu, J. Wu, J. Su, H. Chen, Z. Ke, T. Chiu, J. Hsu, C. Cheng, Y. Chen and 5 other author(s). ISSCC, page 568-570. IEEE, (2024)An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices.J. Hung, Y. Huang, S. Huang, F. Chang, T. Wen, C. Su, W. Khwa, C. Lo, R. Liu, C. Hsieh and 4 other author(s). ISSCC, page 1-3. IEEE, (2022)LYNSU: automated 3D neuropil segmentation of fluorescent images for Drosophila brains.K. Hsu, C. Shih, N. Chen, and C. Lo. Frontiers Neuroinformatics, (2024)

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Disambiguation of "Lo, Chung-Chuan"

Please choose a person to relate this publication to

Chung-Chuan Chen

Shih-yu Chuang

Jen-Yang Chuang

Mei-Ling Chuang

Jing-Jing Chuang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lo, Chung-Chuan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices.

Please choose a person to relate this publication to

Chung-Chuan Chen

Shih-yu Chuang

Jen-Yang Chuang

Mei-Ling Chuang

Jing-Jing Chuang

Other publications of authors with the same name

Disambiguation