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Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.

M. Rasch, C. Mackin, M. Gallo, A. Chen, A. Fasoli, F. Odermatt, N. Li, S. Nandakumar, P. Narayanan, H. Tsai, G. Burr, A. Sebastian, and V. Narayanan. CoRR, (2023)

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Geoffrey Hinds

Geoffrey Coulson

Geoffrey Lund

Geoffrey Davis

Geoffrey Mwachala

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Non-volatile memory as hardware synapse in neuromorphic computing: A first look at reliability issues.R. Shelby, G. Burr, I. Boybat, and C. di Nolfo. IRPS, page 6. IEEE, (2015)Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation.R. Bruce, S. Sarwat, I. Boybat, C. Cheng, W. Kim, S. Nandakumar, C. Mackin, T. Philip, Z. Liu, K. Brew and 21 other author(s). IRPS, page 1-6. IEEE, (2021)Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges.C. Mackin, P. Narayanan, S. Ambrogio, H. Tsai, K. Spoon, A. Fasoli, A. Chen, A. Friz, R. Shelby, and G. Burr. IRPS, page 1-10. IEEE, (2020)Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays.P. Narayanan, L. Sanches, A. Fumarola, R. Shelby, S. Ambrogio, J. Jang, H. Hwang, Y. Leblebici, and G. Burr. ISCAS, page 1-4. IEEE, (2017)Holographic Data Storage.D. Psaltis, and G. Burr. Computer, 31 (2): 52-60 (1998)Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices.K. Spoon, H. Tsai, A. Chen, M. Rasch, S. Ambrogio, C. Mackin, A. Fasoli, A. Friz, P. Narayanan, M. Stanisavljevic and 1 other author(s). Frontiers Comput. Neurosci., (2021)Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited).G. Burr, P. Narayanan, S. Ambrogio, A. Okazaki, H. Tsai, K. Hosokawa, C. Mackin, A. Nomura, T. Yasuda, J. Demarest and 15 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Phase-change random access memory: A scalable technology.S. Raoux, G. Burr, M. Breitwisch, C. Rettner, Y. Chen, R. Shelby, M. Salinga, D. Krebs, S. Chen, H. Lung and 1 other author(s). IBM J. Res. Dev., 52 (4-5): 465-480 (2008)Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique.I. Boybat, C. di Nolfo, S. Ambrogio, M. Bodini, N. Farinha, R. Shelby, P. Narayanan, S. Sidler, H. Tsai, Y. Leblebici and 1 other author(s). ICRC, page 1-8. IEEE, (2017)Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.M. Rasch, C. Mackin, M. Gallo, A. Chen, A. Fasoli, F. Odermatt, N. Li, S. Nandakumar, P. Narayanan, H. Tsai and 3 other author(s). CoRR, (2023)

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Disambiguation of "Burr, Geoffrey W."

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Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.

Please choose a person to relate this publication to

Geoffrey Hinds

Geoffrey Coulson

Geoffrey Lund

Geoffrey Davis

Geoffrey Mwachala

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Burr, Geoffrey W."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.

Please choose a person to relate this publication to

Geoffrey Hinds

Geoffrey Coulson

Geoffrey Lund

Geoffrey Davis

Geoffrey Mwachala

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
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Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.