Author of the publication

Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.

, , , , , , , , , , , , and . CoRR, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Supervised Learning in Spiking Neural Networks with Phase-Change Memory Synapses., , , , , and . CoRR, (2019)Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators., , , , , , , , , and 3 other author(s). CoRR, (2023)Computational memory-based inference and training of deep neural networks., , , , , , , , , and 6 other author(s). VLSI Circuits, page 168-. IEEE, (2019)Live demonstration: Spiking neural circuit based navigation inspired by C. elegans thermotaxis., , , , , , and . ISCAS, page 1905. IEEE, (2015)Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation., , , , , , , , , and 21 other author(s). IRPS, page 1-6. IEEE, (2021)An efficient synaptic architecture for artificial neural networks., , , , , , , , and . NVMTS, page 1-4. IEEE, (2017)Deep learning acceleration based on in-memory computing., , , , , , , , , and 7 other author(s). IBM J. Res. Dev., 63 (6): 7:1-7:16 (2019)HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing., , , , , , , , , and 14 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)Phase-Change Memory Models for Deep Learning Training and Inference., , , , , , , and . ICECS, page 727-730. IEEE, (2019)Impact of conductance drift on multi-PCM synaptic architectures., , , , , , and . NVMTS, page 1-4. IEEE, (2018)