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Disambiguation of "Koike, Hiroki"

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Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability.

, , , , , , , , , , , and . IRPS, page 54-1. IEEE, (2022)

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Hiroki Takahashi

Hiroki Kawamura

Hiroki Sumizawa

Ursula Koike-Good

 

Other publications of authors with the same name

NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors., , , , , , , , , and . IEEE J. Solid State Circuits, 36 (3): 522-527 (2001)An embedded FeRAM macro cell for a smart card microcontroller., , , , , , , , , and 3 other author(s). CICC, page 439-442. IEEE, (1998)An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz., , , , , , , , , and 6 other author(s). ISSCC, page 202-204. IEEE, (2019)FeRAM device and circuit technologies fully compatible with advanced CMOS., , , , , , , , , and 2 other author(s). CICC, page 171-178. IEEE, (2001)A novel memory test system with an electromagnet for STT-MRAM testing., , , , , , and . NVMTS, page 1-4. IEEE, (2019)NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors., , , , , , , , , and . CICC, page 65-68. IEEE, (2000)An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O., , and . IEICE Trans. Electron., 94-C (6): 945-952 (2011)Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design., , , , , , and . ISCAS, page 1878-1881. IEEE, (2016)Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability., , , , , , , , , and 2 other author(s). IRPS, page 54-1. IEEE, (2022)1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times., , , , , , , , and . VLSIC, page 46-47. IEEE, (2012)