Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.

M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi, M. Yasuhira, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu. ISSCC, page 202-204. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hiroaki Kobayashi

Hiroaki Tanaka

Other publications of authors with the same name

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.M. Natsui, A. Tamakoshi, H. Honjo, T. Watanabe, T. Nasuno, C. Zhang, T. Tanigawa, H. Inoue, M. Niwa, T. Yoshiduka and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications.N. Sakimura, Y. Tsuji, R. Nebashi, H. Honjo, A. Morioka, K. Ishihara, K. Kinoshita, S. Fukami, S. Miura, N. Kasai and 4 other author(s). ISSCC, page 184-185. IEEE, (2014)A 90nm 12ns 32Mb 2T1MTJ MRAM.R. Nebashi, N. Sakimura, H. Honjo, S. Saito, Y. Ito, S. Miura, Y. Kato, K. Mori, Y. Ozaki, Y. Kobayashi and 10 other author(s). ISSCC, page 462-463. IEEE, (2009)Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.D. Suzuki, M. Natsui, A. Mochizuki, S. Miura, H. Honjo, H. Sato, S. Fukami, S. Ikeda, T. Endoh, H. Ohno and 1 other author(s). VLSIC, page 172-. IEEE, (2015)High-speed simulator including accurate MTJ models for spintronics integrated circuit design.N. Sakimura, R. Nebashi, Y. Tsuji, H. Honjo, T. Sugibayashi, H. Koike, T. Ohsawa, S. Fukami, T. Hanyu, H. Ohno and 1 other author(s). ISCAS, page 1971-1974. IEEE, (2012)1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Tokutome, S. Ikeda, T. Hanyu, H. Ohno, and T. Endoh. VLSIC, page 46-47. IEEE, (2012)MRAM Cell Technology for Over 500-MHz SoC.N. Sakimura, T. Sugibayashi, T. Honda, H. Honjo, S. Saito, T. Suzuki, N. Ishiwata, and S. Tahara. IEEE J. Solid State Circuits, 42 (4): 830-838 (2007)A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.R. Nebashi, N. Sakimura, H. Honjo, A. Morioka, Y. Tsuji, K. Ishihara, K. Tokutome, S. Miura, S. Fukami, K. Kinoshita and 5 other author(s). ISCAS, page 1588-1591. IEEE, (2014)An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi and 6 other author(s). ISSCC, page 202-204. IEEE, (2019)Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.M. Natsui, D. Suzuki, N. Sakimura, R. Nebashi, Y. Tsuji, A. Morioka, T. Sugibayashi, S. Miura, H. Honjo, K. Kinoshita and 4 other author(s). ISSCC, page 194-195. IEEE, (2013)

BibSonomy

Disambiguation of "Honjo, Hiroaki"

Please choose a person to relate this publication to

Hiroaki Kobayashi

Hiroaki Tanaka

Other publications of authors with the same name

Disambiguation