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Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.

X. Wang, J. Xu, W. Zhang, X. Wu, Y. Ye, Z. Wang, M. Nikdast, and Z. Wang. DATE, page 1221-1224. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Zhehui Wang

Zhehui Luo

Wang Wang

Linfang Wang

Investigation of the functions of 53BP1 in DNA demethylationL. Wang. Uni Marburg, (2009)

Paul Wang

Other publications of authors with the same name

System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.Y. Ye, J. Xu, X. Wu, W. Zhang, X. Wang, M. Nikdast, Z. Wang, and W. Liu. IEEE Trans. Very Large Scale Integr. Syst., 21 (2): 292-305 (2013)RSON: An inter/intra-chip silicon photonic network for rack-scale computing systems.P. Yang, Z. Pang, Z. Wang, Z. Wang, M. Xie, X. Chen, L. Duong, and J. Xu. DATE, page 1369-1374. IEEE, (2018)A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.W. Liu, J. Xu, X. Wang, Y. Wang, W. Zhang, Y. Ye, X. Wu, M. Nikdast, and Z. Wang. ISVLSI, page 260-265. IEEE Computer Society, (2011)Systematic Exploration of High-Radix Integrated Silicon Photonic Switches for Datacenters.Z. Wang, J. Feng, X. Chen, Z. Wang, J. Zhang, S. Chen, and J. Xu. ICCAD, page 1-8. ACM, (2019)Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors.X. Wang, J. Xu, Z. Wang, K. Chen, X. Wu, and Z. Wang. DATE, page 1-4. European Design and Automation Association, (2014)Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore system.Z. Wang, Z. Tian, J. Xu, R. Maeda, H. Li, P. Yang, Z. Wang, L. Duong, Z. Wang, and X. Chen. ASP-DAC, page 684-689. IEEE, (2017)Improve Chip Pin Performance Using Optical Interconnects.Z. Wang, J. Xu, P. Yang, X. Wang, Z. Wang, L. Duong, Z. Wang, R. Maeda, and H. Li. IEEE Trans. Very Large Scale Integr. Syst., 24 (4): 1574-1587 (2016)Scalable Low-Power High-Performance Rack-Scale Optical Network.J. Feng, Z. Wang, Z. Wang, X. Chen, S. Chen, J. Zhang, and J. Xu. PHOTONICS@SC, page 1-6. IEEE, (2019)MOCA: an Inter/Intra-Chip Optical Network for Memory.Z. Wang, Z. Pang, P. Yang, J. Xu, X. Chen, R. Maeda, Z. Wang, L. Duong, H. Li, and Z. Wang. DAC, page 86:1-86:6. ACM, (2017)NCPower: Power Modelling for NVM-based Neuromorphic Chip.Z. Wang, H. Zhang, T. Luo, W. Wong, A. Do, P. Vishnu, W. Zhang, and R. Goh. ICONS, page 15:1-15:7. ACM, (2020)

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Disambiguation of "Wang, Zhehui"

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Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.

Please choose a person to relate this publication to

Zhehui Wang

Zhehui Luo

Wang Wang

Linfang Wang

Paul Wang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wang, Zhehui"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.

Please choose a person to relate this publication to

Zhehui Wang

Zhehui Luo

Wang Wang

Linfang Wang

Paul Wang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.