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Adiabatic flip-flops and sequential circuit design using novel resettable adiabatic buffers., , и . ECCTD, стр. 1-4. IEEE, (2017)Logical effort based power-delay-product optimization., , , и . ICACCI, стр. 565-569. IEEE, (2014)A Memristor-based Tuneable Offset Comparator., , , и . NEWCAS, стр. 1-5. IEEE, (2023)Impact of Adiabatic Logic Families on the Power-Clock Generator Energy Efficiency., и . PRIME, стр. 25-28. IEEE, (2019)A CMOS-based Characterisation Platform for Emerging RRAM Technologies., , , , , , , , , и 4 other автор(ы). ISCAS, стр. 75-79. IEEE, (2022)An Adiabatic Regenerative Capacitive Artificial Neuron., , , и . ISCAS, стр. 1-5. IEEE, (2021)Optimisation of multiperformance characteristics in electric discharge machining of Aluminium Matrix Composites (AMCs) using Taguchi DOE methodology., , и . IJMR, 2 (2): 138-161 (2007)Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout., , , , , , , , , и 1 other автор(ы). IEEE Trans. Circuits Syst. I Regul. Pap., 68 (12): 4876-4888 (2021)Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology., , , и . VDAT, том 382 из Communications in Computer and Information Science, стр. 185-193. Springer, (2013)Characterization of Logical Effort for Improved Delay., , и . VDAT, том 382 из Communications in Computer and Information Science, стр. 108-117. Springer, (2013)