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A 640 Mbit/S 32-Bit Pipelined Implementation of the AES Algorithm., , , и . SECRYPT, стр. 453-459. INSTICC Press, (2008)Shift-Reduce Parsers for Transition Networks., , и . LATA, том 8370 из Lecture Notes in Computer Science, стр. 222-235. Springer, (2014)From Ambiguous Regular Expressions to Deterministic Parsing Automata., , , и . CIAA, том 9223 из Lecture Notes in Computer Science, стр. 35-48. Springer, (2015)Parallel Hardware Architectures for the Cryptographic Tate Pairing., , , и . ITNG, стр. 186-191. IEEE Computer Society, (2006)Exploring Cortex-M Microarchitectural Side Channel Information Leakage., , , и . IEEE Access, (2021)A pairing SW implementation for Smart-Cards., , , , , и . J. Syst. Softw., 81 (7): 1240-1247 (2008)Guest Editors' Introduction: Special Section on Fault Diagnosis and Tolerance in Cryptography., и . IEEE Trans. Computers, 55 (9): 1073-1074 (2006)Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm., , , , и . ASAP, стр. 423-432. IEEE Computer Society, (2003)About the performances of the Advanced Encryption Standard in embedded systems with cache memory., , , , , и . ISCAS (5), стр. 145-148. IEEE, (2003)A model for the evaluation of fault tolerance in the FERMI system., и . DFT, стр. 72-80. IEEE Computer Society, (1995)