Author of the publication

Optimization on cell-library design for digital Application Specific Printed Electronics Circuits.

, , , , and . PATMOS, page 1-6. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Exact Benchmark Circuits for Logic Synthesis., , , , , , and . IEEE Des. Test, 37 (3): 51-58 (2020)Constructive AIG optimization considering input weights., , and . ISQED, page 769-776. IEEE, (2011)Technology Mapping for Circuits with Simple Cells., , and . ISCAS, page 1-5. IEEE, (2018)Efficient method to compute minimum decision chains of Boolean functions., , , and . ACM Great Lakes Symposium on VLSI, page 419-422. ACM, (2011)A comparative study of CMOS gates with minimum transistor stacks., , , , and . SBCCI, page 93-98. ACM, (2007)Tool integration using the web-services approach., , , and . ACM Great Lakes Symposium on VLSI, page 337-340. ACM, (2005)Fast disjoint transistor networks from BDDs., , , , , and . SBCCI, page 137-142. ACM, (2006)SOP based logic synthesis for memristive IMPLY stateful logic., , , and . ICCD, page 228-235. IEEE Computer Society, (2015)SIFU! - A Didactic Stuck-at Fault Simulator., , and . MSE, page 93-94. IEEE Computer Society, (2003)Self-checking test circuits for latches and flip-flops., , , and . IOLTS, page 210-213. IEEE Computer Society, (2011)