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Synthesis of low-power selectively-clocked systems from high-level specification., and . ACM Trans. Design Autom. Electr. Syst., 5 (3): 311-321 (2000)A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only)., , and . FPGA, page 281. ACM, (2016)Optimization of Reliability and Power Consumption in Systems on a Chip., , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 237-246. Springer, (2005)A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control., , , , and . CODES+ISSS, page 130-135. ACM, (2006)Full system for translational studies of personalized medicine with free-moving mice., , , , , , , , , and . ISCAS, page 1774-1777. IEEE, (2015)Evaluating ESOP Optimization Methods in Quantum Compilation Flows., , , , and . RC, volume 11497 of Lecture Notes in Computer Science, page 191-206. Springer, (2019)Scalable Boolean Methods in a Modern Synthesis Flow., , , , , , , , and . DATE, page 1643-1648. IEEE, (2019)Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs., , , , , , and . DATE, page 625-630. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Towards high-performance polarity-controllable FETs with 2D materials., , , , , , , , and . DATE, page 637-641. IEEE, (2018)Performance analysis of 3-D monolithic integrated circuits., , , , , and . 3DIC, page 1-4. IEEE, (2010)