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Disambiguation of "Luo, Jiong"

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Integrated ESOP Refactoring for Industrial Designs.

, , , , , and . ICECS, page 369-372. IEEE, (2018)

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Estelle Jiongo

Jiong Tao

Jiong Tian

Jiong Zhou

Jiong Zhang

 

Other publications of authors with the same name

Improvements to boolean resynthesis., , , , , , , and . DATE, page 755-760. IEEE, (2018)Integrated ESOP Refactoring for Industrial Designs., , , , , and . ICECS, page 369-372. IEEE, (2018)SAT-Sweeping Enhanced for Logic Synthesis., , , , , , , , and . DAC, page 1-6. IEEE, (2020)Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems., and . VLSI Design, page 369-375. IEEE Computer Society, (2003)Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors., , , and . ICCD, page 391-394. IEEE Computer Society, (2002)Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems., , and . ICCAD, page 30-38. IEEE Computer Society / ACM, (2003)Scalable Boolean Methods in a Modern Synthesis Flow., , , , , , , , and . DATE, page 1643-1648. IEEE, (2019)Register binding-based RTL power management for control-flow intensive designs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (8): 1175-1183 (2004)Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems., and . ASP-DAC/VLSI Design, page 719-. IEEE Computer Society, (2002)Improving LUT-based optimization for ASICs., , , , , , and . DAC, page 421-426. ACM, (2022)