( en | de | ru )

 

Disambiguation of "Hassan, Hasan"

Author of the publication

copydeleteadd this publication to your clipboard
Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices.

, , , and . DSN, page 13-25. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Hassan Hasan

Istabrak Hasan

Mahamudul Hasan

Maen Khaled Amin Hasan

Alkomiet Hasan

 

Other publications of authors with the same name

GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies., , , , , , , , , and . BMC Genom., (2018)Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics., , , , and . MICRO, page 282-297. IEEE, (2020)MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations., , , , , , , and . ACM Trans. Archit. Code Optim., 19 (2): 26:1-26:29 (2022)Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators., , , and . ACM Trans. Archit. Code Optim., 18 (1): 2:1-2:29 (2021)Enabling Efficient RDMA-based Synchronous Mirroring of Persistent Memory Transactions., , , , , , , , , and 3 other author(s). CoRR, (2018)Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices., , , and . DSN, page 13-25. IEEE, (2019)Improving DRAM Performance, Reliability, and Security by Rigorously Understanding Intrinsic DRAM Operation.. ETH Zurich, Zürich, Switzerland, (2022)base-search.net (ftethz:oai:www.research-collection.ethz.ch:20.500.11850/601914).HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips., , , , , , , and . MICRO, page 815-834. IEEE, (2022)Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology., , , , , , , , , and . MICRO, page 273-287. ACM, (2017)What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study., , , , , , , , , and 2 other author(s). SIGMETRICS (Abstracts), page 110. ACM, (2018)