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Disambiguation of "Lacaita, Andrea Leonardo"

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17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking.

, , , , , , , and . ISSCC, page 268-270. IEEE, (2020)

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Leonardo Estupiñán

Leonardo Finocchi

Leonardo Dude

Leonardo Ebeling

Leonardo Bianchi

 

Other publications of authors with the same name

A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique., , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2024)10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM., , , , , , , and . ISSCC, page 188-190. IEEE, (2024)A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter., , , , , , , , , and 4 other author(s). ISSCC, page 445-447. IEEE, (2021)A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching., , , , , , , , , and 3 other author(s). ISSCC, page 1-3. IEEE, (2022)10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion., , , , , , , , and . ISSCC, page 198-200. IEEE, (2024)A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS., , , , and . CICC, page 1-2. IEEE, (2021)17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking., , , , , , , and . ISSCC, page 268-270. IEEE, (2020)17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter., , , , , , , and . ISSCC, page 274-276. IEEE, (2020)