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Disambiguation of "Santiccioli, Alessio"

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17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking.

, , , , , , , and . ISSCC, page 268-270. IEEE, (2020)

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Alessio Langiu

Alessio Meneghetti

Alessio Guerri

Alessio Quaglino

Alessio Vascon

 

Other publications of authors with the same name

High-efficiency inductorless frequency synthesis.. Polytechnic University of Milan, Italy, (2020)32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , , , and 5 other author(s). ISSCC, page 456-458. IEEE, (2021)A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter., , , , , , , , , and 4 other author(s). ISSCC, page 445-447. IEEE, (2021)A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler., , , , , , , , , and 3 other author(s). CICC, page 1-2. IEEE, (2022)A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching., , , , , , , , , and 3 other author(s). ISSCC, page 1-3. IEEE, (2022)17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking., , , , , , , and . ISSCC, page 268-270. IEEE, (2020)17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter., , , , , , , and . ISSCC, page 274-276. IEEE, (2020)A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power., , , , and . CICC, page 1-4. IEEE, (2019)