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A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 58 (1): 291-302 (2023)

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A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application., , , , , , , , , and 27 other author(s). IEEE J. Solid State Circuits, 58 (1): 291-302 (2023)A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization., , , , , , , , , and 39 other author(s). ISSCC, page 444-446. IEEE, (2022)13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry., , , , , , , , , and 14 other author(s). ISSCC, page 232-234. IEEE, (2024)A 1.1V 16Gb DDR5 DRAM with Probabilistic-Aggressor Tracking, Refresh-Management Functionality, Per-Row Hammer Tracking, a Multi-Step Precharge, and Core-Bias Modulation for Security and Reliability Enhancement., , , , , , , , , and 27 other author(s). ISSCC, page 414-415. IEEE, (2023)13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction., , , , , , , , , and 20 other author(s). ISSCC, page 246-248. IEEE, (2024)A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization., , , , , , , , , and 29 other author(s). IEEE J. Solid State Circuits, 58 (1): 256-269 (2023)A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications., , , , , , , , , and 21 other author(s). ISSCC, page 1-3. IEEE, (2022)A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques., , , , , , , , , and 10 other author(s). CICC, page 1-4. IEEE, (2014)A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications., , , , , , , , , and 11 other author(s). ISSCC, page 210-212. IEEE, (2018)13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization., , , , , , , , , and 38 other author(s). ISSCC, page 238-240. IEEE, (2024)