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A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.

A. Wang, W. Bae, J. Han, S. Bailey, P. Rigge, O. Ocal, Z. Wang, K. Ramchandran, E. Alon, and B. Nikolic. ESSCIRC, page 322-325. IEEE, (2018)

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Luyang Han

Muxin Han

Mei Han

Johannes Han

Bing Han

Other publications of authors with the same name

A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.J. Han, E. Chang, S. Bailey, Z. Wang, W. Bae, A. Wang, N. Narevsky, A. Whitcombe, P. Lu, B. Nikolic and 1 other author(s). CICC, page 1-4. IEEE, (2019)A 32-Gb/s High-Swing PAM-4 Current-Mode Driver with Current-Bleeding Cascode Technique and Capacitive-Coupled Pre-drivers in 40-nm CMOS for Short-Reach Wireline Communications.E. Song, J. Yang, S. Hong, and J. Han. MWSCAS, page 1-4. IEEE, (2022)Non-blind Image Deconvolution using Sampling without Replacement.J. Han, J. Kim, and M. Kang. Image Processing: Algorithms and Systems, page 125-130. Society for Imaging Science and Technology, (2017)Analysis of Grounded Coplanar Waveguide (GCPW) for High-Speed Links Channel.Y. Oh, T. Sim, and J. Han. ISOCC, page 117-118. IEEE, (2023)Multi-Frame Depth Super-Resolution for ToF Sensor With Total Variation Regularized L1 Function.J. Kim, J. Han, and M. Kang. IEEE Access, (2020)BAG2: A process-portable framework for generator-based AMS circuit design.E. Chang, J. Han, W. Bae, Z. Wang, N. Narevsky, B. Nikolic, and E. Alon. CICC, page 1-8. IEEE, (2018)An Analysis of CMOS Latched Comparators.S. Yeom, T. Sim, and J. Han. ICEIC, page 1-4. IEEE, (2023)Multi-frame super-resolution utilizing spatially adaptive regularization for ToF camera.H. Lee, J. Kim, J. Han, and M. Kang. Image Processing: Algorithms and Systems, Society for Imaging Science and Technology, (2019)Multi-Phase Frequency Divider Generator with Process-Independent Automation.J. Jang, H. Jeong, and J. Han. ISOCC, page 129-130. IEEE, (2023)8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS.M. Choi, Z. Wang, K. Lee, K. Park, Z. Liu, A. Biswas, J. Han, and E. Alon. ISSCC, page 128-130. IEEE, (2021)

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Disambiguation of "Han, Jaeduk"

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A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.

Please choose a person to relate this publication to

Luyang Han

Muxin Han

Mei Han

Johannes Han

Bing Han

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Han, Jaeduk"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.

Please choose a person to relate this publication to

Luyang Han

Muxin Han

Mei Han

Johannes Han

Bing Han

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.