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Disambiguation of "Bae, Woo-Rham"

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A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.

, , , , , , , , , , and . CICC, page 1-4. IEEE, (2019)

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Jin-Woo Bae

Seong-Woo Bae

Ulrich Rhamm

Gérard de Rham

Soonil Bae

 

Other publications of authors with the same name

A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS., , and . ISCAS, page 1869-1872. IEEE, (2014)A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control., , and . CICC, page 1-4. IEEE, (2017)BAG2: A process-portable framework for generator-based AMS circuit design., , , , , , and . CICC, page 1-8. IEEE, (2018)A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm., , , , , , , , and . A-SSCC, page 1-4. IEEE, (2015)A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET., , , , , , , , , and 21 other author(s). A-SSCC, page 285-288. IEEE, (2018)A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection., , , , , , , , , and . ESSCIRC, page 384-387. IEEE, (2015)A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 2691-2702 (2018)4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET., , , , , , , , , and 2 other author(s). ISSCC, page 58-60. IEEE, (2021)A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme., , , and . ISCAS, page 2346-2349. IEEE, (2016)A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line., , , , , and . ESSCIRC, page 447-450. IEEE, (2014)