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A simple technique for locating gate-level faults in combinational circuits.

, , и . Asian Test Symposium, стр. 65-70. IEEE Computer Society, (1995)

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Edward J Birkenbeil

Edward J Birkenbeil

Edward J Laarman

Edward Hartstein

Edward Dotzel

 

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An Experimental Study Comparing 74LS181 Test Sets., , и . COMPCON, стр. 384-387. IEEE Computer Society, (1985)Built-In Verification Test.. ITC, стр. 183-190. IEEE Computer Society, (1982)An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-at Fault Test Sets., и . ITC, стр. 52-58. IEEE Computer Society, (1984)Test Teaching.. ITC, стр. 235. IEEE Computer Society, (1985)IC Quality and Test Transparency., и . ITC, стр. 295-301. IEEE Computer Society, (1988)Refined Bounds on Signature Analysis Aliasing for Random Testing., , и . ITC, стр. 818-827. IEEE Computer Society, (1991)Verification testing.. DAC, стр. 495-500. ACM/IEEE, (1982)Designing CMOS Circuits for Switch-Level Testability., и . IEEE Des. Test, 4 (4): 42-49 (1987)Reconfigurable Architecture for Autonomous Self-Repair., , , , и . IEEE Des. Test Comput., 21 (3): 228-240 (2004)Iterative Combinational Switching Networksߞ General Design Considerations.. IRE Trans. Electron. Comput., 7 (4): 285-291 (1958)