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Optimization of Equational Specifications Using Genetic Techniques.

, , , , и . DSD, стр. 252-258. IEEE Computer Society, (2002)

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Humberto Jorge José

Nadine José Gonzalez

José Baena

José Teixeira

José Izquierdo

 

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Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis., , , и . PATMOS, том 2799 из Lecture Notes in Computer Science, стр. 617-627. Springer, (2003)Formal Techniques for Hardware Allocation., , и . VLSI Design, стр. 161-165. IEEE Computer Society, (1997)Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis., , , и . DSD, стр. 308-315. IEEE Computer Society, (2002)A global approach to improve conditional hardware reuse in high-level synthesis., , и . J. Syst. Archit., 47 (12): 959-975 (2002)Bit-level scheduling of heterogeneous behavioural specifications., , и . ICCAD, стр. 602-608. ACM / IEEE Computer Society, (2002)Power optimization in heterogenous datapaths., , , , и . DATE, стр. 1400-1405. IEEE, (2011)A Unified Algorithm for Mutual Exclusiveness Identification., , и . EUROMICRO, стр. 1504-1510. IEEE Computer Society, (1999)Multiple-Precision Circuits Allocation Independent of Data-Objects Length., , и . DATE, стр. 909-913. IEEE Computer Society, (2002)Maximizing Conditonal Reuse by Pre-Synthesis Transformations., , и . DATE, стр. 1097. IEEE Computer Society, (2002)Pre-synthesis optimization of multiplications to improve circuit performance., , , и . DATE, стр. 1306-1311. European Design and Automation Association, Leuven, Belgium, (2006)