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Optimization of Equational Specifications Using Genetic Techniques.

, , , , and . DSD, page 252-258. IEEE Computer Society, (2002)

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Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis., , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 617-627. Springer, (2003)Formal Techniques for Hardware Allocation., , and . VLSI Design, page 161-165. IEEE Computer Society, (1997)Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis., , , and . DSD, page 308-315. IEEE Computer Society, (2002)A global approach to improve conditional hardware reuse in high-level synthesis., , and . J. Syst. Archit., 47 (12): 959-975 (2002)Bit-level scheduling of heterogeneous behavioural specifications., , and . ICCAD, page 602-608. ACM / IEEE Computer Society, (2002)A Unified Algorithm for Mutual Exclusiveness Identification., , and . EUROMICRO, page 1504-1510. IEEE Computer Society, (1999)Power optimization in heterogenous datapaths., , , , and . DATE, page 1400-1405. IEEE, (2011)Arrival time aware scheduling to minimize clock cycle length., , , and . ASP-DAC, page 1018-1021. ACM Press, (2005)Multiple-Precision Circuits Allocation Independent of Data-Objects Length., , and . DATE, page 909-913. IEEE Computer Society, (2002)Maximizing Conditonal Reuse by Pre-Synthesis Transformations., , and . DATE, page 1097. IEEE Computer Society, (2002)