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Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET., , , , , , , , , and 2 other author(s). ESSCIRC, page 183-186. IEEE, (2017)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , and 5 other author(s). ISSCC, page 476-478. IEEE, (2019)4×40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS., , , , , , , , , and 6 other author(s). OFC, page 1-3. IEEE, (2018)Using 3D integration technology to realize multi-context FPGAs., , , , , , and . FPL, page 507-510. IEEE, (2009)3D configuration caching for 2D FPGAs., , , , , , and . FPGA, page 286. ACM, (2009)DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology., , , , , , , , , and 1 other author(s). ESSCIRC, page 115-118. IEEE, (2017)Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver., , , , , , , , , and 3 other author(s). ISCAS, page 1-5. IEEE, (2018)A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET., , , , , , , , , and 6 other author(s). A-SSCC, page 239-240. IEEE, (2019)Design space exploration for field programmable compressor trees., , , , , , and . CASES, page 207-216. ACM, (2008)3D serial TSV link for low-power chip-to-chip communication., , , and . ICICDT, page 1-4. IEEE, (2014)