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Disambiguation of "Hamada, Mototsugu"

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A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm.

, , , , , , , , , , , , , and . ISSCC, page 326-327. IEEE, (2010)

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Sandra Hamada

Taha Auf Hamada

Mahmoud Ahmed Hamada

Azhari Abdelazim Hamada

Hamada Dahy Hussein Mahboub

 

Other publications of authors with the same name

A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier., , , , , , and . ISSCC, page 214-215. IEEE, (2008)A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 456-457. IEEE, (2010)Wireless power transfer to stacked modules for IoT sensor nodes., , , , and . ISOCC, page 59-60. IEEE, (2017)A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI., , , , , , , , , and 1 other author(s). CICC, page 527-530. IEEE, (2005)A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS., , , and . ASP-DAC, page 97-98. ACM, (2021)A 5.2GHz RFID Chip Contactlessly Mountable on FPC at any 90-Degree Rotation and Face Orientation., , , , , and . ASP-DAC, page 5-6. IEEE, (2022)A Fully Synthesized 13.7μJ/Prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network., , , , , and . ASP-DAC, page 182-183. ACM, (2023)A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes., , , , , , , , and . ISCAS, page 1-5. IEEE, (2020)A 0.13mJ/Prediction CIFAR-100 Raster-Scan- Based Wired-Logic Processor Using Non-Linear Neural Network., , , , , and . ISCAS, page 1-5. IEEE, (2023)A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver., , , , and . IEEE J. Solid State Circuits, 58 (7): 2075-2086 (2023)