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Disambiguation of "Teh, Chen Kong"

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A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI.

, , , , , , , , , , and . CICC, page 527-530. IEEE, (2005)

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Shou-Kong Chen

Teh Amouh

Thay Kong

Xiangqing Kong

Seunghyun Kong

 

Other publications of authors with the same name

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology., , , , , , , , , and 12 other author(s). ISSCC, page 262-263. IEEE, (2008)12.3 A 2-output step-up/step-down switched-capacitor DC-DC converter with 95.8% peak efficiency and 0.85-to-3.6V input voltage range., and . ISSCC, page 222-223. IEEE, (2016)4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control., , , , and . ISSCC, page 78-79. IEEE, (2014)An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer., , , , , , , , , and 43 other author(s). ISSCC, page 442-444. IEEE, (2018)A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI., , , , , , , , , and 1 other author(s). CICC, page 527-530. IEEE, (2005)A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS., , , and . ISSCC, page 338-340. IEEE, (2011)Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (12): 1379-1383 (2006)