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Designing Efficient Memory for Future Computing Systems.

. University of Utah, USA, (2012)

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Aniruddha Nazre

Aniruddha Marathe

Aniruddha Kembhavi

Aniruddha Jayant Deshpande

 

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CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems., , , , , , , , , и 3 other автор(ы). ISCA, стр. 39:1-39:17. ACM, (2023)Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy., , , , , , , и . HPCA, стр. 262-274. IEEE Computer Society, (2009)Designing Efficient Memory for Future Computing Systems.. University of Utah, USA, (2012)Simulating DRAM controllers for future system architecture exploration., , , , и . ISPASS, стр. 201-210. IEEE Computer Society, (2014)Rethinking DRAM design and organization for energy-constrained multi-cores., , , , , и . ISCA, стр. 175-186. ACM, (2010)LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems., , , , и . ISCA, стр. 285-296. IEEE Computer Society, (2012)Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device., , , , , и . MICRO, стр. 198-209. ACM, (2013)Non-uniform power access in large caches with low-swing wires., , и . HiPC, стр. 59-68. IEEE Computer Society, (2009)Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems., , , , и . ISCA, стр. 425-436. ACM, (2011)Towards scalable, energy-efficient, bus-based on-chip networks., , и . HPCA, стр. 1-12. IEEE Computer Society, (2010)