( en | de | ru )

 

Disambiguation of "Chu, Thiem Van"

Author of the publication

copydeleteadd this publication to your clipboard
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation.

, , , , , , and . CANDAR, page 215-220. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Thiem Le Van

Chu Van Chi

La Van Chu

Van Trung Chu

NULL Le van Thiem

 

Other publications of authors with the same name

Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs., , and . FPGA, page 211-221. ACM, (2020)A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems., , , , , , and . IEICE Trans. Inf. Syst., 106 (12): 1969-1978 (December 2023)A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning., , , , and . FPT, page 1-10. IEEE, (2021)ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation., , , , , , and . CANDAR, page 215-220. IEEE, (2020)Multicoated and Folded Graph Neural Networks With Strong Lottery Tickets., , , , , , , and . LoG, volume 231 of Proceedings of Machine Learning Research, page 11. PMLR, (2023)Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization., , , , and . GECCO, ACM, (2024)The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs., , , and . NOCS, page 1-8. IEEE, (2016)Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension., , , , , , , , , and 2 other author(s). ISSCC, page 42-43. IEEE, (2023)A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath., , , , and . FCCM, page 197-204. IEEE Computer Society, (2018)Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA., , and . FCCM, page 60-63. IEEE Computer Society, (2015)