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Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA.

, , , , , and . IPDPS Workshops, page 450-459. IEEE, (2020)

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An HDL-synthesized gated-edge-injection PLL with a current output DAC., , , , , , and . ASP-DAC, page 2-3. IEEE, (2015)High-productivity Programming and Optimization Framework for Stream Processing on FPGA., , , and . HEART, page 5:1-5:6. ACM, (2018)FPGA-Dedicated Network vs. Server Network for Pipelined Computing with Multiple FPGAs., , and . HEART, page 90-91. ACM, (2022)A Productive HLS Simulation Approach for Multi-FPGA Systems., , , , and . ICCE, page 1-2. IEEE, (2024)Hybrid Network Utilization for Efficient Communication in a Tightly Coupled FPGA Cluster., , , and . FPT, page 363-366. IEEE, (2019)Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC., , , , , , , and . IPDPS Workshops, page 452-459. IEEE, (2023)ESSPER: Elastic and Scalable System for High-Performance Reconfigurable Computing with Software-bridged APIs., , , and . FPT, page 1. IEEE, (2022)25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation., , , , , , , , , and 5 other author(s). A-SSCC, page 109-112. IEEE, (2016)Bandwidth compression of multiple numerical data streams for high performance custom computing., , , and . ASAP, page 190-191. IEEE Computer Society, (2014)