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Predicting die-level process variations from wafer test data for analog devices: A feasibility study.

, , , , , and . LATW, page 1-6. IEEE Computer Society, (2013)

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Predicting die-level process variations from wafer test data for analog devices: A feasibility study., , , , , and . LATW, page 1-6. IEEE Computer Society, (2013)Variation and failure characterization through pattern classification of test data from multiple test stages., , , , , , and . ITC, page 1-10. IEEE, (2016)IC laser trimming speed-up through wafer-level spatial correlation modeling., , , , , , and . ITC, page 1-7. IEEE Computer Society, (2014)Parametric counterfeit IC detection via Support Vector Machines., , and . DFT, page 7-12. IEEE Computer Society, (2012)Spatial correlation modeling for probe test cost reduction in RF devices., , , and . ICCAD, page 23-29. ACM, (2012)A fast spatial variation modeling algorithm for efficient test cost reduction of analog/RF circuits., , , , , and . DATE, page 1042-1047. ACM, (2015)Handling discontinuous effects in modeling spatial correlation of wafer-level analog/RF tests., , , and . DATE, page 553-558. EDA Consortium San Jose, CA, USA / ACM DL, (2013)On combining alternate test with spatial correlation modeling in analog/RF ICs., , , and . ETS, page 1-6. IEEE Computer Society, (2013)Quality improvement and cost reduction using statistical outlier methods., , , and . ICCD, page 64-69. IEEE Computer Society, (2009)Die-level adaptive test: Real-time test reordering and elimination., , , , and . ITC, page 1-10. IEEE Computer Society, (2011)