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15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips., , , , , , , , , и 17 other автор(ы). ISSCC, стр. 246-248. IEEE, (2020)A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors., , , , , , , , , и 6 other автор(ы). A-SSCC, стр. 217-218. IEEE, (2019)A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 396-398. IEEE, (2019)34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices., , , , , , , , , и 8 other автор(ы). ISSCC, стр. 580-582. IEEE, (2024)A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W., , , , , , , , , и 6 other автор(ы). ISSCC, стр. 258-259. IEEE, (2023)15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips., , , , , , , , , и 13 other автор(ы). ISSCC, стр. 240-242. IEEE, (2020)A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training., , , , , , , , , и . DAC, стр. 1-6. IEEE, (2020)8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips., , , , , , , , , и 11 other автор(ы). IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2304-2308 (апреля 2024)Test points selection process and diagnosability analysis of analog integrated circuits., и . ICCD, стр. 582-587. IEEE Computer Society, (1998)A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors., , , , , , , , , и 8 other автор(ы). IEEE J. Solid State Circuits, 55 (10): 2790-2801 (2020)