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A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.

H. Jiang, S. Huang, X. Peng, J. Su, Y. Chou, W. Huang, T. Liu, R. Liu, M. Chang, and S. Yu. DAC, page 1-6. IEEE, (2020)

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Wei Liu

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15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.J. Su, X. Si, Y. Chou, T. Chang, W. Huang, Y. Tu, R. Liu, P. Lu, T. Liu, J. Wang and 13 other author(s). ISSCC, page 240-242. IEEE, (2020)15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices.C. Xue, T. Huang, J. Liu, T. Chang, H. Kao, J. Wang, T. Liu, S. Wei, S. Huang, W. Wei and 10 other author(s). ISSCC, page 244-246. IEEE, (2020)A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices.C. Xue, J. Hung, H. Kao, Y. Huang, S. Huang, F. Chang, P. Chen, T. Liu, C. Jhang, C. Su and 8 other author(s). ISSCC, page 245-247. IEEE, (2021)15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.X. Si, Y. Tu, W. Huang, J. Su, P. Lu, J. Wang, T. Liu, S. Wu, R. Liu, Y. Chou and 17 other author(s). ISSCC, page 246-248. IEEE, (2020)16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.J. Su, Y. Chou, R. Liu, T. Liu, P. Lu, P. Wu, Y. Chung, L. Hung, J. Ren, T. Pan and 11 other author(s). ISSCC, page 250-252. IEEE, (2021)A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.H. Jiang, S. Huang, X. Peng, J. Su, Y. Chou, W. Huang, T. Liu, R. Liu, M. Chang, and S. Yu. DAC, page 1-6. IEEE, (2020)8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.J. Su, P. Lu, P. Wu, Y. Chou, T. Liu, Y. Chung, L. Hung, J. Ren, W. Huang, C. Chien and 11 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 71 (4): 2304-2308 (April 2024)

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Disambiguation of "Liu, Ta-Wei"

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A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.

Please choose a person to relate this publication to

Wei Liu

Wei Liu

Wei Liu

Wei Liu

Wei Liu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Liu, Ta-Wei"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.

Please choose a person to relate this publication to

Wei Liu

Wei Liu

Wei Liu

Wei Liu

Wei Liu

Other publications of authors with the same name

Disambiguation

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URL
DOI
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Chicago
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A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.