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A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.

H. Jiang, S. Huang, X. Peng, J. Su, Y. Chou, W. Huang, T. Liu, R. Liu, M. Chang, and S. Yu. DAC, page 1-6. IEEE, (2020)

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Xiaochen Hu

Xiaochen Lian

Changgeng Peng

Xiao-Wei Peng

Martin Peng

Other publications of authors with the same name

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning.P. Chen, X. Peng, and S. Yu. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3067-3080 (2018)XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption.S. Huang, H. Jiang, X. Peng, W. Li, and S. Yu. ICCAD, page 77:1-77:6. IEEE, (2020)Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator.P. Wang, X. Peng, W. Chakraborty, A. Khan, S. Datta, and S. Yu. ISCAS, page 1-4. IEEE, (2021)Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices.S. Huang, X. Sun, X. Peng, H. Jiang, and S. Yu. ACM Trans. Design Autom. Electr. Syst., 27 (4): 37:1-37:19 (2022)Compute-in-Memory: From Device Innovation to 3D System Integration.S. Yu, W. Shim, J. Hur, Y. chun Luo, G. Choe, W. Li, A. Lu, and X. Peng. ESSDERC, page 21-28. IEEE, (2021)Benchmark Framework for 2-D/3-D Integrated Compute-in-Memory Based Machine Learning Accelerator.X. Peng. Georgia Institute of Technology, Atlanta, GA, USA, (2022)base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/66465).A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator.A. Lu, X. Peng, Y. Luo, S. Huang, and S. Yu. DATE, page 932-937. IEEE, (2021)CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training.H. Jiang, X. Peng, S. Huang, and S. Yu. MEMSYS, page 490-496. ACM, (2019)Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis.W. Zhang, X. Peng, H. Wu, B. Gao, H. He, Y. Zhang, S. Yu, and H. Qian. DAC, page 140. ACM, (2019)Parallelizing SRAM arrays with customized bit-cell for binary neural networks.R. Liu, X. Peng, X. Sun, W. Khwa, X. Si, J. Chen, J. Li, M. Chang, and S. Yu. DAC, page 21:1-21:6. ACM, (2018)

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Disambiguation of "Peng, Xiaochen"

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A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.

Please choose a person to relate this publication to

Xiaochen Hu

Xiaochen Lian

Changgeng Peng

Xiao-Wei Peng

Martin Peng

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Peng, Xiaochen"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.

Please choose a person to relate this publication to

Xiaochen Hu

Xiaochen Lian

Changgeng Peng

Xiao-Wei Peng

Martin Peng

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.