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Automatic generation of loop scheduling for VLIW., , , и . PACT, стр. 306-309. IFIP Working Group on Algol / ACM, (1995)Runtime-assisted cache coherence deactivation in task parallel programs., , , , и . SC, стр. 35:1-35:12. IEEE / ACM, (2018)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , и . International Conference on Supercomputing, стр. 12-19. ACM, (1997)Dynamic Tolerance Region Computing for Multimedia., , и . IEEE Trans. Computers, 61 (5): 650-665 (2012)A performance evaluation of the multiple bus network for multiprocessor systems., , , , и . SIGMETRICS, стр. 200-206. ACM, (1983)Novel SRAM bias control circuits for a low power L1 data cache., , , , и . NORCHIP, стр. 1-6. IEEE, (2012)RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only)., , , , , и . SIGMETRICS Perform. Evaluation Rev., 39 (3): 19 (2011)Evolutionary system for prediction and optimization of hardware architecture performance., , , , , , , и . IEEE Congress on Evolutionary Computation, стр. 1941-1948. IEEE, (2008)VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations., , , , , , , , и . HPCA, стр. 921-934. IEEE, (2021)VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing., , , , , , , и . HPCA, стр. 1289-1302. IEEE, (2023)