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A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection.

S. Cho, S. Kim, M. Choo, H. Ko, J. Lee, W. Bae, и D. Jeong. IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 2691-2702 (2018)

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Han-Bong Ko

Zun-Gon Kim

Hyung-Gon Jeong

Kim Se Gon

Insok Ko

Другие публикации лиц с тем же именем

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation.S. Lee, H. Ko, J. Chae, S. Shin, J. Yun, D. Jeong, и S. Kim. IEEE Trans. Circuits Syst. II Express Briefs, 67-II (10): 1735-1739 (2020)0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link.W. Lee, M. Shim, Y. Lee, H. Yang, H. Ko, W. Choi, и D. Jeong. ESSCIRC, стр. 475-478. IEEE, (2021)A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection.S. Cho, S. Kim, M. Choo, J. Lee, H. Ko, S. Jang, S. Chu, W. Bae, Y. Kim, и D. Jeong. ESSCIRC, стр. 384-387. IEEE, (2015)A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection.S. Cho, S. Kim, M. Choo, H. Ko, J. Lee, W. Bae, и D. Jeong. IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (9): 2691-2702 (2018)A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop.M. Choo, H. Ko, S. Cho, K. Lee, и D. Jeong. A-SSCC, стр. 73-76. IEEE, (2018)A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS.J. Park, H. Lee, H. Cho, S. Lee, K. Lee, H. Ko, и D. Jeong. ISSCC, стр. 410-411. IEEE, (2023)A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop.H. Ko, S. Shin, C. Kye, S. Lee, J. Yun, H. Jung, D. Lee, S. Kim, и D. Jeong. VLSI Circuits, стр. 94-. IEEE, (2019)A theoretical analysis of phase shift in pulse injection-locked oscillators.J. Lee, S. Kim, M. Choo, S. Cho, H. Ko, и D. Jeong. ISCAS, стр. 1662-1665. IEEE, (2016)6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS.K. Park, M. Shim, H. Ko, и D. Jeong. ISSCC, стр. 124-126. IEEE, (2020)A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller.J. Park, K. Lee, Y. Lee, J. Sull, Y. Song, S. Lee, H. Lee, H. Cho, J. Oh, H. Ko и 1 other автор(ы). VLSI Technology and Circuits, стр. 150-151. IEEE, (2022)

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