( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization.

, , , , , , , , и . ISSCC, стр. 164-165. IEEE, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Matteo Garavoglia

Matteo Rini

Matteo Gabba

Marco Matteo

Matteo Bertini

 

Другие публикации лиц с тем же именем

A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS., , , и . ISSCC, стр. 216-217. IEEE, (2008)A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators., , , , , , , , и . ISSCC, стр. 220-221. IEEE, (2010)22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s., , , , , , и . ISSCC, стр. 1-3. IEEE, (2015)A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4., , , , , , и . ESSCIRC, стр. 221-224. IEEE, (2012)A 3.2-to-7.3GHz Quadrature Oscillator with Magnetic Tuning., , , и . ISSCC, стр. 92-589. IEEE, (2007)12.2 A 4-Channel 200Gb/s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications., , , , , , , , , и 10 other автор(ы). ISSCC, стр. 210-212. IEEE, (2020)A Low-Noise Design Technique for High-Speed CMOS Optical Receivers., , , , , , и . IEEE J. Solid State Circuits, 49 (6): 1437-1447 (2014)A sliding IF receiver for mm-wave WLANs in 65nm CMOS., , , , , , и . CICC, стр. 669-672. IEEE, (2009)A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies., , , , , и . ESSCIRC, стр. 131-134. IEEE, (2014)A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication., , , , , , , , , и . IEEE J. Solid State Circuits, 44 (4): 1306-1315 (2009)