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Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack.

M. Li, L. Lai, V. Chandra, и D. Pan. DAC, стр. 17:1-17:6. ACM, (2017)

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David Tse-chien Pan

Z Taufig

Petra Pan

Xiaoqing Pan

Weiqing Pan

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On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes.K. Shamsi, T. Meade, M. Li, D. Pan, и Y. Jin. IEEE Trans. Inf. Forensics Secur., 14 (2): 347-359 (2019)Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography.B. Yu, X. Xu, J. Gao, Y. Lin, Z. Li, C. Alpert, и D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 726-739 (2015)Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization.K. Yuan, J. Yang, и D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (2): 185-196 (2010)Redundant Local-Loop Insertion for Unidirectional Routing.X. Xu, Y. Lin, M. Li, J. Ou, B. Cline, и D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (7): 1113-1125 (2017)OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions.S. Roy, D. Liu, J. Singh, J. Um, и D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (10): 1618-1629 (2016)MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.Y. Lin, B. Yu, X. Xu, J. Gao, N. Viswanathan, W. Liu, Z. Li, C. Alpert, и D. Pan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (6): 1237-1250 (2018)A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier.X. Tang, X. Yang, W. Zhao, C. Hsu, J. Liu, L. Shen, A. Mukherjee, W. Shi, S. Li, D. Pan и 1 other автор(ы). IEEE J. Solid State Circuits, 55 (12): 3248-3259 (2020)A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier.X. Tang, X. Yang, J. Liu, Z. Wang, W. Shi, D. Pan, и N. Sun. IEEE J. Solid State Circuits, 58 (9): 2564-2574 (сентября 2023)An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback.S. Li, D. Pan, и N. Sun. IEEE J. Solid State Circuits, 55 (5): 1337-1350 (2020)Machine learning for IC design and technology co-optimization in extreme scaling.D. Pan. VLSI-DAT, стр. 1. IEEE, (2018)

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