( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?

, , , , , , , , , , , , , , , , , , и . ESSCIRC, стр. 84-87. IEEE, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Abdelkarim Habib

Abdelkarim Omar

Abdelkarim Mouhssine

Abdelkarim Kerbaa

Abdelkarim Belhoula

 

Другие публикации лиц с тем же именем

Technologies for (sub-) 45nm Analog/RF CMOS - Circuit Design Opportunities and Challenges., , , , и . CICC, стр. 679-686. IEEE, (2006)Holisitic device exploration for 7nm node., , , , , , , , , и 5 other автор(ы). CICC, стр. 1-5. IEEE, (2015)Analysis of microbump induced stress effects in 3D stacked IC technologies., , , , , , , , , и 9 other автор(ы). 3DIC, стр. 1-5. IEEE, (2011)Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM., , , , , , , и . ICICDT, стр. 1-4. IEEE, (2015)A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS., , , , , , , , , и . IEEE J. Solid State Circuits, 40 (7): 1434-1442 (2005)Technology and architecture for deep submicron RF CMOS technology.. SBCCI, стр. 4. ACM, (2005)STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process., , , , , , , , и . ESSDERC, стр. 159-162. IEEE, (2013)Identifying the Bottlenecks to the RF Performance of FinFETs., , , , , , и . VLSI Design, стр. 111-116. IEEE Computer Society, (2010)A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS., , , , , , , , , и . ESSCIRC, стр. 291-294. IEEE, (2004)Low-cost feedback-enabled LNAs in 45nm CMOS., , , , и . ESSCIRC, стр. 100-103. IEEE, (2009)