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RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs.

J. Nguyen, D. Turgis, D. Bonciani, B. Lhomme, Y. Carminati, O. Callen, G. Guirleo, L. Ciampolini, and G. Ghibaudo. NATW, page 28-33. IEEE, (2016)

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Lorenzo Ciampolini

Lorenzo Cubillos

Lorenzo Pettazzi

Lorenzo Zani

Lorenzo Guiducci

Other publications of authors with the same name

Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI.K. Akyel, L. Ciampolini, O. Thomas, B. Pelloux-Prayer, S. Kumar, P. Flatresse, C. Lecocq, and G. Ghibaudo. ISCAS, page 1452-1455. IEEE, (2013)Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI.F. Abouzeid, A. Bienfait, K. Akyel, A. Feki, S. Clerc, L. Ciampolini, F. Giner, R. Wilson, and P. Roche. IEEE J. Solid State Circuits, 49 (7): 1499-1505 (2014)A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI.B. Mohammadi, O. Andersson, J. Nguyen, L. Ciampolini, A. Cathelin, and J. Rodrigues. ESSCIRC, page 429-432. IEEE, (2016)Storage Class Memory with Computing Row Buffer: A Design Space Exploration.V. Egloff, J. Noel, M. Kooli, B. Giraud, L. Ciampolini, R. Gauchi, C. Tortolero, E. Guthmuller, M. Moreau, and J. Portal. DATE, page 1-6. IEEE, (2021)Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI.F. Abouzeid, A. Bienfait, K. Akyel, S. Clerc, L. Ciampolini, and P. Roche. ESSCIRC, page 205-208. IEEE, (2013)Efficient yield estimation through generalized importance sampling with application to NBL-assisted SRAM bitcells.L. Ciampolini, J. Lafont, F. Drissi, J. Morin, D. Turgis, X. Jonsson, C. Desclèves, and J. Nguyen. ICCAD, page 89. ACM, (2016)RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs.J. Nguyen, D. Turgis, D. Bonciani, B. Lhomme, Y. Carminati, O. Callen, G. Guirleo, L. Ciampolini, and G. Ghibaudo. NATW, page 28-33. IEEE, (2016)Impact of Random Telegraph Signals on 6T high-density SRAM in 28nm UTBB FD-SOI.K. Akyel, L. Ciampolini, O. Thomas, D. Turgis, and G. Ghibaudo. ESSDERC, page 94-97. IEEE, (2014)Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.S. Clerc, F. Abouzeid, D. Patel, J. Daveau, C. Bottoni, L. Ciampolini, F. Giner, D. Meyer, R. Wilson, P. Roche and 4 other author(s). ISQED, page 366-370. IEEE, (2015)28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications.R. Ranica, N. Planes, V. Huard, O. Weber, D. Noblet, D. Croain, F. Giner, S. Naudet, P. Mergault, S. Ibars and 11 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)

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Disambiguation of "Ciampolini, Lorenzo"

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RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs.

Please choose a person to relate this publication to

Lorenzo Ciampolini

Lorenzo Cubillos

Lorenzo Pettazzi

Lorenzo Zani

Lorenzo Guiducci

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ciampolini, Lorenzo"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs.

Please choose a person to relate this publication to

Lorenzo Ciampolini

Lorenzo Cubillos

Lorenzo Pettazzi

Lorenzo Zani

Lorenzo Guiducci

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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RAPIDO Testing and Modeling of Assisted Write and Read Operations for SRAMs.