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Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory.

K. Lee, S. Tanikawa, M. Murugesan, H. Naganuma, J. Bea, T. Fukushima, T. Tanaka, and M. Koyanagi. 3DIC, page 1-4. IEEE, (2013)

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Wolfgang Bea

Bea Klüsener

Bea Harazd

Bea Kastner

Wolfgang Bea

Other publications of authors with the same name

3D memory chip stacking by multi-layer self-assembly technology.T. Fukushima, J. Bea, M. Murugesan, H. Son, M. Suh, K. Byun, N. Kim, K. Lee, and M. Koyanagi. 3DIC, page 1-4. IEEE, (2013)Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature.T. Fukushima, E. Iwata, J. Bea, M. Murugesan, K. Lee, T. Tanaka, and M. Koyanagi. 3DIC, page 1-5. IEEE, (2010)High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs.K. Lee, J. Bea, T. Fukushima, Y. Ohara, T. Tanaka, and M. Koyanagi. 3DIC, page 1-4. IEEE, (2011)Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV.M. Murugesan, J. Bea, K. Lee, T. Fukushima, T. Tanaka, M. Koyanagi, Y. Sutou, H. Wang, and J. Koike. 3DIC, page 1-4. IEEE, (2013)Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory.K. Lee, S. Tanikawa, M. Murugesan, H. Naganuma, J. Bea, T. Fukushima, T. Tanaka, and M. Koyanagi. 3DIC, page 1-4. IEEE, (2013)Temporary bonding strength control for self-assembly-based 3D integration.T. Fukushima, Y. Ohara, J. Bea, M. Murugesan, K. Lee, T. Tanaka, and M. Koyanagi. 3DIC, page 1-4. IEEE, (2011)10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack.Y. Ohara, A. Noriki, K. Sakuma, K. Lee, M. Murugesan, J. Bea, F. Yamada, T. Fukushima, T. Tanaka, and M. Koyanagi. 3DIC, page 1-6. IEEE, (2009)Development of via-last 3D integration technologies using a new temporary adhesive system.T. Fukushima, J. Bea, M. Murugesan, K. Lee, and M. Koyanagi. 3DIC, page 1-4. IEEE, (2013)Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding.M. Murugesan, Y. Ohara, J. Bea, K. Lee, T. Fukushima, T. Tanaka, and M. Koyanagi. 3DIC, page 1-5. IEEE, (2010)Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI.A. Noriki, K. Lee, J. Bea, T. Fukushima, T. Tanaka, and M. Koyanagi. 3DIC, page 1-4. IEEE, (2011)

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Disambiguation of "Bea, Jichoel"

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Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory.

Please choose a person to relate this publication to

Wolfgang Bea

Bea Klüsener

Bea Harazd

Bea Kastner

Wolfgang Bea

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Bea, Jichoel"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory.

Please choose a person to relate this publication to

Wolfgang Bea

Bea Klüsener

Bea Harazd

Bea Kastner

Wolfgang Bea

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory.