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A 67mW D-band FMCW I/Q Radar Receiver with an N-path Spillover Notch Filter in 28nm CMOS.

, , , , , , and . ESSCIRC, page 471-474. IEEE, (2021)

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Digital Ground Bounce Reduction by Phase Modulation of the Clock., , , , , and . DATE, page 88-93. IEEE Computer Society, (2004)A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS., , , , and . IEEE J. Solid State Circuits, 54 (2): 403-416 (2019)Digital ground bounce reduction by supply current shaping and clock frequency Modulation., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (1): 65-76 (2005)A 247 and 272 GHz Two-Stage Regenerative Amplifiers in 65 nm CMOS with 18 and 15 dB Gain Based on Double-Gmax Gain Boosting Technique., , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)A flexible power model for mm-wave and THz high-throughput communication systems., , , , and . PIMRC, page 1-6. IEEE, (2020)A 28 nm CMOS 7.04 Gsps polar digital front-end processor for 60 GHz transmitter., , , , , , , , , and . A-SSCC, page 333-336. IEEE, (2016)A Single-Package Solution for Wireless Transceivers., , , , , and . DATE, page 425-. IEEE Computer Society / ACM, (1999)Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients., , , , , , and . DAC, page 399-404. ACM, (2002)Flicker noise upconversion mechanisms in K-band CMOS VCOs., , , and . A-SSCC, page 1-4. IEEE, (2015)A Compact K-band, Asymmetric Coupler-based, Switchless Transmit-Receive Front-End in 0.15μm GaN-on-SiC Technology., , , , and . ESSCIRC, page 457-460. IEEE, (2023)