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Disambiguation of "Huisman, Leendert M."

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TRIM: testability range by ignoring the memory.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (1): 38-49 (1988)

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Marc Huisman

Leendert Bliek

Leendert Molendijk

Leendert Euser

Brent Huisman

 

Other publications of authors with the same name

SLS - a fast switch level simulator for verification and fault coverage analysis., , , , and . DAC, page 164-170. IEEE Computer Society Press, (1986)Analysis and Design of Optimal Combinational Compactors., and . VTS, page 101-106. IEEE Computer Society, (2003)Diagnosis and characterization of timing-related defects by time-dependent light emission., , , , , , , , , and 1 other author(s). ITC, page 733-739. IEEE Computer Society, (1998)Correlations between path delays and the accuracy of performance prediction.. ITC, page 801-808. IEEE Computer Society, (1998)Fault simulation of logic designs on parallel processors with distributed memory., and . ITC, page 690-697. IEEE Computer Society, (1990)Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm., , , and . ITC, page 287-296. IEEE Computer Society, (2001)Diagnosing arbitrary defects in logic designs using single location at a time (SLAT).. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (1): 91-101 (2004)Symbolic implication in test generation., , , and . EURO-DAC, page 492-496. EEE Computer Society, (1991)Data Mining Integrated Circuit Fails with Fail Commonalities., , and . ITC, page 661-668. IEEE Computer Society, (2004)TRIM: testability range by ignoring the memory., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (1): 38-49 (1988)