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SLS - a fast switch level simulator for verification and fault coverage analysis., , , , и . DAC, стр. 164-170. IEEE Computer Society Press, (1986)Analysis and Design of Optimal Combinational Compactors., и . VTS, стр. 101-106. IEEE Computer Society, (2003)Diagnosis and characterization of timing-related defects by time-dependent light emission., , , , , , , , , и 1 other автор(ы). ITC, стр. 733-739. IEEE Computer Society, (1998)Correlations between path delays and the accuracy of performance prediction.. ITC, стр. 801-808. IEEE Computer Society, (1998)Fault simulation of logic designs on parallel processors with distributed memory., и . ITC, стр. 690-697. IEEE Computer Society, (1990)Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm., , , и . ITC, стр. 287-296. IEEE Computer Society, (2001)Symbolic implication in test generation., , , и . EURO-DAC, стр. 492-496. EEE Computer Society, (1991)Diagnosing arbitrary defects in logic designs using single location at a time (SLAT).. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (1): 91-101 (2004)Data Mining Integrated Circuit Fails with Fail Commonalities., , и . ITC, стр. 661-668. IEEE Computer Society, (2004)TRIM: testability range by ignoring the memory., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (1): 38-49 (1988)