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The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing.

, , , and . ICRC, page 1-8. IEEE, (2017)

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A Power Model for Register-Sharing Structures., and . DIPES, volume 271 of IFIP, page 131-142. Springer, (2008)Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors., , and . HiPC, volume 2228 of Lecture Notes in Computer Science, page 192-203. Springer, (2001)Qwerty: A Basis-Oriented Quantum Programming Language., , , and . CoRR, (2024)System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design., , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (2): 129-137 (2000)Parallel Pattern Detection for Architectural Improvements., , and . HotPar, USENIX Association, (2011)Experimental Insights from the Rogues Gallery., , , , , and . ICRC, page 80-87. IEEE, (2019)Computationally-redundant energy-efficient processing for y'all (CREEPY)., , , , , , and . ICRC, page 1-8. IEEE Computer Society, (2016)Energy efficiency limits of logic and memory., , , , , , , , , and . ICRC, page 1-8. IEEE Computer Society, (2016)Iterative Modulo Scheduling., , , and . IEEE Micro, 38 (1): 115-117 (2018)High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm., and . IEEE Trans. Parallel Distributed Syst., 16 (12): 1132-1142 (2005)