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Disambiguation of "Saitoh, Masumi"

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Novel Operation Scheme for Suppressing Disturb in HfO2-based FeFET Considering Charge- Trapping-Coupled Polarization Dynamics.

, , , , , , , , , , and . IRPS, page 1-5. IEEE, (2023)

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Masumi Kersken

Masumi Shimizu

Masumi Morita

 

Other publications of authors with the same name

Emerging Non-Volatile Memory and Thin-Film Transistor Technologies for Future 3D-LSI., , , , , , , , and . ESSDERC, page 138-141. IEEE, (2018)Comprehensive Analysis of Hole-Trapping in SiN Films with a Wide Range of Time Constants Based on Dynamic C-V., , , , , and . IRPS, page 1-7. IEEE, (2023)Hot carrier degradation, TDDB, and 1/f noise in Poly-Si Tri-gate nanowire transistor., , and . IRPS, page 5. IEEE, (2018)Emerging nanoscale silicon devices taking advantage of nanostructure physics., , and . IBM J. Res. Dev., 50 (4-5): 411-418 (2006)A Vertical Channel-All-Around FeFET with Thermally Stable Oxide Semiconductor Achieving High ΔIon> 2µA/cell for 3D Stackable 4F2 High Speed Memory., , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2024)Impact of specific failure mechanisms on endurance improvement for HfO2-based ferroelectric tunnel junction memory., , , , , , , , and . IRPS, page 6. IEEE, (2018)Cycling Induced Imprint Phenomenon at Intermediate State used for Multi-Level Operation in HfO2-FeFET., , , , , , , and . IRPS, page 1-5. IEEE, (2025)Ag Ionic Memory Cell Technology for Terabit-Scale High-DensityApplication., , , , , , , , , and . VLSI Circuits, page 188-. IEEE, (2019)New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering., , and . ESSDERC, page 258-261. IEEE, (2015)Novel Operation Scheme for Suppressing Disturb in HfO2-based FeFET Considering Charge- Trapping-Coupled Polarization Dynamics., , , , , , , , , and 1 other author(s). IRPS, page 1-5. IEEE, (2023)