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A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing., , , , , , and . CoRR, (2024)ALPINE: Analog In-Memory Acceleration with Tight Processor Integration for Deep Learning., , , , , , , , and . CoRR, (2022)Neuromorphic computing with multi-memristive synapses., , , , , , , , , and . CoRR, (2017)Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited)., , , , , , , , , and 13 other author(s). ISCAS, page 1-5. IEEE, (2023)Architecting more than Moore: wireless plasticity for massive heterogeneous computer architectures (WiPLASH)., , , , , , , , , and 12 other author(s). CF, page 191-193. ACM, (2021)A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh., , , , , , , , , and 5 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 31 (1): 114-127 (2023)Non-volatile memory as hardware synapse in neuromorphic computing: A first look at reliability issues., , , and . IRPS, page 6. IEEE, (2015)Equivalent-accuracy accelerated neural-network training using analogue memory., , , , , , , , , and 4 other author(s). Nat., 558 (7708): 60-67 (2018)An efficient synaptic architecture for artificial neural networks., , , , , , , , and . NVMTS, page 1-4. IEEE, (2017)End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture., , , , , , and . DATE, page 1-6. IEEE, (2023)