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Monitoring optical modulation amplitude using a low-power CMOS circuit for thermal control of Si ring transmitters., , , , , , and . ECOC, page 1-3. IEEE, (2014)Mitigating substrate leakage loss on a monolithic SiPh platform: experimental demonstration of hybrid Si-SiN waveguides for O-band datacom., , , , , , , , , and 18 other author(s). OFC, page 1-3. IEEE, (2024)Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC., , , , , and . DSD, page 729-734. IEEE Computer Society, (2008)45nm CMOS - Silicon Photonics Monolithic Technology (45CLO) for Next-Generation, Low Power and High Speed Optical Interconnects., , , , , , , , , and 12 other author(s). OFC, page 1-3. IEEE, (2020)Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?, , , , , , , , , and 9 other author(s). ESSCIRC, page 84-87. IEEE, (2009)High Performance Avalanche Photodiode in a Monolithic Silicon Photonics Technology., , , , , , , , , and 21 other author(s). OFC, page 1-3. IEEE, (2022)Automatic Waveguide Balancing Using Point Set Operations., , , , , , , , , and 1 other author(s). OFC, page 1-3. IEEE, (2022)Monolithically integrated self-aligned SiN edge coupler with 520 mW high-power handling capability., , , , , , , , , and 36 other author(s). OFC, page 1-3. IEEE, (2023)Design issues and considerations for low-cost 3D TSV IC technology., , , , , , , , , and 24 other author(s). ISSCC, page 148-149. IEEE, (2010)3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)., , , , , , , , , and 3 other author(s). 3DIC, page 1-5. IEEE, (2009)