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Disambiguation of "Hirabayashi, Daiki"

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Multi-bit sigma-delta TDC architecture with self-calibration.

, , , , , , , , , , , , and . APCCAS, page 671-674. IEEE, (2012)

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Other publications of authors with the same name

A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS., , , , , and . ASP-DAC, page 553-554. IEEE, (2012)Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements., , , , , , and . ISOCC, page 146-149. IEEE, (2011)Multi-bit Sigma-Delta TDC Architecture with Improved Linearity., , , , , , , , , and 3 other author(s). J. Electron. Test., 29 (6): 879-892 (2013)Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges., , , , , , , and . ASP-DAC, page 103-104. IEEE, (2013)A clock jitter reduction circuit using gated phase blending between self-delayed clock edges., , , , , , , and . VLSIC, page 142-143. IEEE, (2012)A CMOS PWM Transceiver Using Self-Referenced Edge Detection., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (6): 1145-1149 (2015)Multi-bit sigma-delta TDC architecture with self-calibration., , , , , , , , , and 3 other author(s). APCCAS, page 671-674. IEEE, (2012)