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CoDeNet: Algorithm-hardware Co-design for Deformable Convolution., , , , , , , and . CoRR, (2020)HAWQV3: Dyadic Neural Network Quantization., , , , , , , , , and 1 other author(s). CoRR, (2020)HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference., , , , , and . FCCM, page 50-59. IEEE, (2021)AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs., , , , and . DATE, page 490-495. IEEE, (2020)Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim., , and . EMC2@HPCA/CVPR/ISCA, page 21-25. IEEE, (2019)Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs., , , , , , , , , and 1 other author(s). CoRR, (2018)Co-design ofAlgorithms, Hardware, and Scheduling for Deep Learning Applications. University of California, Berkeley, USA, (2021)DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators., , , , and . MICRO, page 209-224. ACM, (2023)Full Stack Optimization of Transformer Inference: a Survey., , , , , , , , , and 2 other author(s). CoRR, (2023)BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors., , and . RTAS, page 364-375. IEEE, (2020)