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AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs., , , , and . DATE, page 490-495. IEEE, (2020)HAWQV3: Dyadic Neural Network Quantization., , , , , , , , , and 1 other author(s). CoRR, (2020)The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware., , , , , , , and . ACM Trans. Reconfigurable Technol. Syst., 8 (3): 14:1-14:26 (2015)HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference., , , , , and . FCCM, page 50-59. IEEE, (2021)CoDeNet: Algorithm-hardware Co-design for Deformable Convolution., , , , , , , and . CoRR, (2020)Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs., , , , , , , , , and 1 other author(s). CoRR, (2018)Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim., , and . EMC2@HPCA/CVPR/ISCA, page 21-25. IEEE, (2019)Co-design ofAlgorithms, Hardware, and Scheduling for Deep Learning Applications. University of California, Berkeley, USA, (2021)FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud., , , , , , , , , and 6 other author(s). ISCA, page 29-42. IEEE Computer Society, (2018)CoSA: Scheduling by Constrained Optimization for Spatial Accelerators., , , , , , , and . ISCA, page 554-566. IEEE, (2021)