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State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit.

, , , and . APCCAS, page 607-610. IEEE, (2012)

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State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit., , , and . APCCAS, page 607-610. IEEE, (2012)A delay variation and floorplan aware high-level synthesis algorithm with body biasing., , , and . ISQED, page 75-80. IEEE, (2016)A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures., , , and . SoCC, page 7-12. IEEE, (2015)MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures., , , and . IEICE Electron. Express, 9 (17): 1414-1422 (2012)Throughput driven check point selection in suspicious timing error prediction based designs., , , and . LASCAS, page 1-4. IEEE, (2014)GECOM: Test data compression combined with all unknown response masking., , , and . ASP-DAC, page 577-582. IEEE, (2008)VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding., , , , and . APCCAS, page 1139-1142. IEEE, (2010)An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction., , , and . APCCAS, page 300-303. IEEE, (2014)An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages., , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard., , , and . ISCAS, page 149-152. IEEE, (2007)