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Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing.

, , , и . APCCAS, стр. 639-642. IEEE, (2014)

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Michitaka Ota

Shin'ichi Kameyama

 

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Latency Minimization of Parallel VLSI Processors for Robotics Using Integer Programming., и . J. Robotics Mechatronics, 6 (2): 143-149 (1994)Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators., , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (12): 2658-2669 (2015)Low-power multiple-valued current-mode integrated circuit with current-source control and its application., , и . ASP-DAC, стр. 413-418. IEEE, (1997)An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture., , , и . ASP-DAC, стр. 89-90. IEEE, (2011)Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit., , , и . ISCAS, стр. 3017-3020. IEEE, (2012)Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products., и . ICRA, стр. 3691-3696. IEEE Computer Society, (1998)A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment., и . APCCAS, стр. 1803-1806. IEEE, (2006)Bayesian Network for algorithm selection: Real-world hierarchy for nodes reduction., и . iCAST/UMEDIA, стр. 69-75. IEEE, (2013)Verification Based Algorithm Selection., и . IDT, стр. 25-30. IEEE, (2023)Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors., , и . ISVLSI, стр. 193-198. IEEE Computer Society, (2006)