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Power and Area Minimization for Multidimensional Signal Processing., , and . IEEE J. Solid State Circuits, 42 (4): 922-934 (2007)Guest Editorial Introduction to the Special Issue on the 2022 Symposium on VLSI Circuits., and . IEEE J. Solid State Circuits, 58 (4): 897-900 (2023)An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors., , , and . IEEE J. Solid State Circuits, 45 (4): 843-855 (2010)BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS., , , , and . IEEE Micro, 39 (2): 52-60 (2019)A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI., , , , , , , , , and 1 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2721-2725 (2020)LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (3): 1012-1022 (2021)Silicon Process Technology Constraints for Standardized Vertical Die-to-Die Interconnects., , , and . CICC, page 1-6. IEEE, (2023)Hammer: a modular and reusable physical design flow tool: invited., , , , , , , , , and . DAC, page 1335-1338. ACM, (2022)Digital integrated circuits- A design perspective, , and . Prentice Hall, 2ed edition, (2004)Simpler, more efficient design.. ESSCIRC, page 20-25. IEEE, (2015)